1. Field of the Invention
The present invention relates generally to processor to processor communications of digital data over a plurality of data lines, and more particularly to the provision of a novel technique for bit-by-bit error detection and correction of transmitted digital errors while reducing software protocol, minimizing transmitter-receiver hardware and relaying any detected error back to the transmitting processor upon its occurrence for correction, and the inhibiting of further data transmission until such detected error is corrected.
2. Description of the Prior Art
With the increasing use of telecommunication techniques for transmission of data in multiprocessor systems, and to and from remote terminals, an ever increasing amount of data must be transmitted from one data processor to another with suitable error detecting and correcting capability provided for detecting and correcting data errors "on the fly" occurring in transmission in a full duplex environment.
One such full duplex system of the prior art having a serial bit-by-bit protocol is referred to by IBM as synchronous data link control (SDLC), and is utilized widely as a teleprocessing procedure in distributed data processing systems. Error correction in an SDLC system is on a formatted basis with a variable number of data bytes per block of data, resulting in a variable block length and in a delayed error correction, as an entire byte or data word must be transmitted before an error can be detected. In the present invention, errors are detected bit-by-bit and corrected word-by-word in the bit stream, not ten to fifteen bits downstream, as in some prior art systems, or after transmission of an entire data block.
U.S. Pat. No. 3,912,872 describes a multiplexing technique for using each data bit transmitted for both message and address information. Other error correction methods of the prior art wherein error detection and correction are accomplished on other than a bit-by-bit basis are U.S. Pat. Nos. 3,680,053; 3,754,217 and 3,378,820.